1. Field of the Invention
The present invention relates to a semiconductor chip package for packaging a semiconductor chip.
2. Description of the Related Art
In the electronics market, demands for portable systems are drastically increasing. To meet such increasing demands, slim and lightweight components must be mounted in those systems.
To realize such slim and lightweight components, there are needs for a technique for reducing a size of individual devices, a system-on-chip (SOC) technique for integrating a plurality of individual devices into one chip, and a system-in-package (SIP) technique for integrating a plurality of devices into one package.
FIG. 1A is a cross-sectional view illustrating an example of a related art semiconductor chip package. Referring to FIG. 1A, a related art semiconductor chip package 10 includes at least one chip 12 flip-chip bonded onto a substrate 11 by using a plurality of bump balls 13, and a metal can 15 formed of a metallic material on the substrate 11. The metal can 15 protects the chip 12 and a passive component from the external environment. Also, the metal can 15 prevents high-frequency signals generating during chip operation from affecting an adjacent package, or blocks external harmful electromagnetic waves.
FIG. 1B is a cross-sectional view illustrating another example of a related art semiconductor chip package. Referring to FIG. 1B, a related art semiconductor chip package 20 includes at least one chip 22 wire-bonded onto a substrate 21 by using a plurality of metal wires 23, and a metal can 25 formed of a metallic material on the substrate 21. The metal can 25 protects the chip 22 and a passive component 24 from the external environment. Also, the metal can 25 prevents high-frequency signals generating during chip operation from affecting an adjacent package, or blocks external harmful electromagnetic waves.
Undescribed reference numerals 16 and 26 in FIGS. 1A and 1B indicate main boards on which the semiconductor chip packages 10 and 20 are mounted, respectively.
In the related art semiconductor chip packages 10 and 20, the passive components 14 and 24 such as a resistor, a capacitor and a coil are mounted on the substrates 11 and 21 besides the chips 12 and 22, and the metal cans 15 and 25 are also mounted on the substrates 11 and 21 to shield the chips 11 and 22 and the passive component 14 and 24 from the external environment. For this reason, the related art semiconductor chip packages 10 and 20 have limitations in that assembly processes of the semiconductor chips 10 and 20 are complicated and take long time to complete, lowering operational productivity. Also, miniaturization of the semiconductor chip packages 10 and 20 is limited because of the metal cans 15 and 25.
Also, the substrates 11 and 21 must include separate ground lines (not shown) electrically connected with ground terminals of the chips 12 and 22, and separate ground lines (not shown) electrically connected with the metal cans 15 and 25 mounted thereon. Hence, the substrate structure is complicated, increasing manufacturing costs.